Trench semiconductor device layout configurations

ABSTRACT

A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of U.S. Provisional Application No. 62/119,555 filed Feb. 23, 2015 for “Trench Semiconductor Device Layout Configurations” by D. Dosev et al.

Incorporation By Reference

U.S. Provisional Application No. 62/119,555 is hereby incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to geometric layouts of trench semiconductor devices.

In many semiconductor devices, such as modern power MOSFET devices, it is desirable for the device to provide a high breakdown voltage that prevents reverse biasing and avalanche breakdown of the diode barriers of the device. In these devices, application of a reverse bias voltage across a diode barrier creates a depletion region in which the voltage gradient present there causes acceleration of charge carriers and the formation of electron-hole pairs by collisions between the charge carriers and dopant atoms. The electron-hole pairs generally migrate to opposite sides of the depletion region; however, higher levels of reverse bias voltage create higher electric fields in the depletion region, which accelerate the electron-hole pairs to a degree that results in further collisions that form further electron-hole pairs. This multiplication of charge carriers can eventually result in conduction of current in the reverse direction across the diode barrier, which is the condition known as avalanche breakdown of the device.

One technique that has been successfully employed to increase the breakdown voltage of a MOSFET device is to form the device as a trench semiconductor device. A trench semiconductor device consists of a plurality of parallel, interior MOS trenches formed in a semiconductor layer, with each trench being lined with dielectric material and then filled with a conductive material such as metal or doped polysilicon. In addition, an exterior trench is formed around an outside region of the device, having at least a portion generally perpendicular to the interior trenches. The gaps between the trenches effectively terminate the electric fields that tend to converge at the edges of the conductive legs formed in each trench, which results in a higher breakdown voltage. U.S. Pat. No. 6,683,363 illustrates an example of a trench semiconductor device.

Further developments in the geometry of a trench semiconductor device can provide characteristics and results that advance the state of the art, such as in terms of performance, cost, space efficiency, or others, or to simply provide an alternative configuration that may be appropriate for selected applications.

SUMMARY

A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material. Various embodiments of the trench semiconductor device with unique trench patterns are disclosed. The various trench patterns provide configurations and/or performance characteristics that may be suitable for particular applications of the devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top plan view of a MOSFET device formed as a trench semiconductor device according to an embodiment of the present invention.

FIG. 1B is a perspective view of the MOSFET device shown in FIG. 1A, sectioned at line B-B in FIG. 1A.

FIGS. 2-16 are top plan views of MOSFET devices formed as trench semiconductor devices according to various embodiments of the present invention.

FIG. 7A is a graph illustrating the measured breakdown voltages of a MOSFET device according to the embodiment of FIG. 7 for various dimensions of trench corner width and exterior trench gap length.

FIG. 8A is a graph illustrating the measured breakdown voltages of a MOSFET device according to the embodiment of FIG. 8 for various dimensions of gap distance and exterior trench length.

DETAILED DESCRIPTION

FIG. 1A is a top plan view of MOSFET device 10 formed as a trench semiconductor device according to an embodiment of the present invention. FIG. 1B is a perspective view of MOSFET device 10 sectioned at line B-B in FIG. 1A. As shown in FIGS. 1A and 1B, MOSFET device 10 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. A metal layer (not shown) is formed over the entire structure, so that a metal/semiconductor barrier is formed where the metal layer adjoins the mesa regions of semiconductor layer 12 between interior trenches 14.

As best illustrated in FIG. 1A, interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 2 micrometers (pm), trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIGS. 2-16 are top plan views of MOSFET devices formed as trench semiconductor devices with alternative trench patterns. Only top plan views of these embodiments are shown, for simplicity, as the nature of the perspective view of each embodiment (similar to that shown in FIG. 1B) will be apparent to those skilled in the art based on the configuration illustrated in the corresponding top plan view. A fill pattern is used in FIGS. 2-16 to illustrate the trench patterns, for ease of understanding.

FIG. 2 is a top plan view of MOSFET device 20 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 20 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of closed rectangles, enclosed by exterior trench 16. In the pattern shown, the sides of each closed rectangle formed by interior trenches 14 are separated from one another by interior gap distance G_(I). Each interior trench 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 3 is a top plan view of MOSFET device 30 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 30 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, intermediate trench 16 a formed in semiconductor layer 12, and exterior trench 16 b formed in semiconductor layer 12. Interior trenches 14, intermediate trench 16 a and exterior trench 16 b are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern enclosed by intermediate trench 16 a, and intermediate trench 16 a is enclosed by exterior trench 16 b. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from intermediate trench 16 a by gap distance G_(E). Intermediate trench 16 a is separated from exterior trench 16 b by gap distance G_(T).

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, gap distance G_(E) may be about 2 μm, and gap distance G_(T) may be about 2 μm.

FIG. 4 is a top plan view of MOSFET device 40 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 40 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and segmented exterior trench 16 having gaps 42 therein formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern partially enclosed by segmented exterior trench 16. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E). Gaps 42 in segmented exterior trench 16 have a gap length G_(O).

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, gap distance G_(E) may be about 2 μm, and gap length G_(O) may be about 2 μm.

FIG. 5 is a top plan view of MOSFET device 50 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 50 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 having notch features 52 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E). Notch features 52 in exterior trench 16 are formed adjacent to openings between the legs of the snake pattern of interior trench 14, and each notch feature has an extending width W_(N).

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, gap distance G_(E) may be about 2 μm, and extending width W_(N) may be about 0.5 μm.

FIG. 6 is a top plan view of MOSFET device 60 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 60 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern having an outer frame and a plurality of vertical trench legs connecting the top and bottom horizontal segments of the outer frame. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Interior trenches 14 have a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 7 is a top plan view of MOSFET device 70 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 70 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and segmented exterior trench 16 having gaps 72 therein formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Interior trenches 14 have a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E). Gaps 72 in segmented exterior trench 16 have a gap length G_(O).

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, gap distance G_(E) may be about 2 μm, gap length G_(O) may be about 1.7 μm, and trench corner width W_(C) may be about 1.5 μm. In other embodiments, these dimensions may be adjusted to control the breakdown voltage at the termination of MOSFET device 70. FIG. 7A is a graph illustrating the measured breakdown voltages of MOSFET device 70 for various dimensions of trench corner width W_(C) and exterior trench gap length G_(O). As can be seen in FIG. 7A, the dimensions of trench corner width W_(C) and exterior trench gap length G_(O) affect the breakdown voltage of the device, and can be controlled in order to provide a desired breakdown voltage value.

Specific examples are shown in FIG. 7A, illustrating that a breakdown voltage of 117 Volts was achieved for an embodiment with exterior trench gap length G_(O) of 0.7 μm and a trench corner width W_(C) of 2.5 μm. A similar breakdown voltage of 117 Volts was also achieved for an embodiment with an exterior trench gap length G_(O) of 1.0 μm and a trench corner width W_(C) of 2.2 μm. A breakdown voltage of 118 Volts was achieved for an embodiment with an exterior trench gap length G_(O) of 1.25 μm and a trench corner width W_(C) of 2.2 μm. At an exterior trench gap length G_(O) of 1.5 μm, a breakdown voltage of 112 Volts was achieved for an embodiment with a trench corner width W_(C) of 1.5 μm, a breakdown voltage of 117 Volts was achieved for an embodiment with a trench corner width W_(C) of 2.0 μm, and a breakdown voltage of 118 Volts was achieved for an embodiment with a trench corner width W_(C) of 2.2 μm. A breakdown voltage of 121 Volts was achieved for an embodiment with an exterior trench gap length G_(O) of 2.0 μm and a trench corner width W_(C) of 2.2 μm.

FIG. 8 is a top plan view of MOSFET device 80 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 80 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and segmented exterior trench 16 having gaps 82 therein formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Interior trenches 14 have a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E). Gaps 82 in segmented exterior trench 16 have a gap length G_(O). Exterior trench 16 is segmented in the embodiment shown in FIG. 8 so that the segments of exterior trench 16 line up with the legs of interior trench 14.

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, gap distance G_(E) may be about 2 μm, and exterior trench length L_(T) may be about 2 μm. In other embodiments, these dimensions may be adjusted to control the breakdown voltage at the termination of MOSFET device 80. FIG. 8A is a graph illustrating the measured breakdown voltages of MOSFET device 80 for various dimensions of gap distance G_(E) and exterior trench length L_(T). As can be seen in FIG. 8A, the dimensions of gap distance G_(E) and exterior trench length L_(T) affect the breakdown voltage of the device, and can be controlled in order to provide a desired breakdown voltage value.

Specific examples are shown in FIG. 8A, illustrating that a breakdown voltage of 114 Volts was achieved for an embodiment with a gap distance G_(E) of 1.0 μm and an exterior trench length L_(T) of 2.5 μm. A similar breakdown voltage of 114 Volts was also achieved for an embodiment with a gap distance G_(E) of 1.5 μm and an exterior trench length L_(T) of 2.5 μm. At a gap distance G_(E) of 2.0 μm, a breakdown voltage of 109 Volts was achieved for an embodiment with an exterior trench length L_(T) of 3.5 μm, and a breakdown voltage of 111 Volts was achieved for an embodiment with an exterior trench length L_(T) of 5.0 μm. A breakdown voltage of 111 Volts was achieved for an embodiment with a gap distance G_(E) of 2.5 μm and exterior trench length L_(T) of 2.5 μm. A breakdown voltage of 112 Volts was achieved for an embodiment with a gap distance G_(E) of 3.0 μm and exterior trench length L_(T) of 2.5 μm, and also for an embodiment with a gap distance G_(E) of 3.5 μm and exterior trench length L_(T) of 2.5 μm.

FIG. 9 is a top plan view of MOSFET device 90 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 90 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a snake pattern enclosed by exterior trench 16. The snake pattern is angled diagonally within exterior trench 16 as shown in FIG. 9. In the snake pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by a minimum gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 2 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 10 is a top plan view of MOSFET device 100 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 100 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a grid pattern enclosed by exterior trench 16. In the grid pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 4.5 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 11 is a top plan view of MOSFET device 110 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 110 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a grid pattern enclosed by exterior trench 16. In the grid pattern, the legs of interior trenches 14 are separated from one another by interior gap distance G_(I). The vertical legs of interior trenches 14 extend beyond a square/rectangular grid pattern at vertical trench extensions 112. Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 4.5 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 12 is a top plan view of MOSFET device 120 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 120 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Interior trenches 14 have a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E). Exterior trench 16 has a trench width that is greater than the trench width W_(T) of interior trenches 14, such as twice the trench width W_(T) in an exemplary embodiment.

In an exemplary embodiment, gap distance G_(I) may be about 2.0 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 13 is a top plan view of MOSFET device 130 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 130 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Middle dividing trench 136 is also formed in semiconductor layer 12, dividing the interior region inside exterior trench 16 into two separate regions, each of which includes a plurality of interior trenches 14. Interior trenches 14, exterior trench 16 and middle dividing trench 136 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a pattern of vertical trench legs. In the pattern shown, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Interior trenches 14 have a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 2.0 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 14 is a top plan view of MOSFET device 140 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 140 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in an offset grid pattern enclosed by exterior trench 16, as shown in FIG. 14. In the grid pattern, the vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I), as are adjacent horizontal legs of interior trenches 14. Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, gap distance G_(I) may be about 4.5 μm, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 15 is a top plan view of MOSFET device 150 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 150 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a honeycomb pattern enclosed by exterior trench 16, as shown in FIG. 15. In the honeycomb pattern, adjacent vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

FIG. 16 is a top plan view of MOSFET device 160 formed as a trench semiconductor device according to another embodiment of the present invention. MOSFET device 160 includes semiconductor layer 12, a plurality of interior trenches 14 formed in semiconductor layer 12, and exterior trench 16 formed in semiconductor layer 12. Interior trenches 14 and exterior trench 16 are lined with dielectric material 18, such as silicon dioxide in some embodiments, and the dielectric lined trenches are filled with a conductive material (not shown) such as a metal or doped polysilicon. Interior trenches 14 are formed in a geometric trench pattern formed of six sided polygons and eight sided polygons enclosed by exterior trench 16, as shown in FIG. 16. In the geometric trench pattern, adjacent vertical legs of interior trenches 14 are separated from one another by interior gap distance G_(I). Each leg of interior trenches 14 has a trench width W_(T), and interior trenches 14 are spaced from exterior trench 16 by gap distance G_(E).

In an exemplary embodiment, trench width W_(T) may be about 1.4 μm, and gap distance G_(E) may be about 2 μm.

The embodiments of the present invention disclosed herein include geometric features that can be mixed and matched with any other disclosed embodiments. For example, the segmented outer trench 16 shown in FIG. 7 may be used with the snake trench pattern shown in FIG. 1A in an alternative embodiment. Other features may also be combined and modified to form additional alternative embodiments and configurations.

In many of the embodiments disclosed herein, modifications of the dimensions of trenches or other features, as well as of gaps between trenches or other features, are able to be modified in order to adjust the performance of the device, such as the breakdown voltage of the device. Examples of such modifications and the resulting performance adjustments are discussed specifically with respect to the embodiments of FIGS. 7 and 8, and modifications to others of the disclosed embodiments will also result in performance adjustments that may be selected and optimized for a particular application.

While the invention has been described with reference to an exemplary embodiment(s), it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the description herein. 

1. A trench semiconductor device comprising: a layer of semiconductor material; an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material; and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of first interior trench portions and a plurality of second interior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of first interior trench portions being arranged perpendicular to the plurality of second interior trench portions with each of the plurality of first interior trench portions being connected to at least one of the plurality of second interior trench portions.
 2. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a snake pattern.
 3. The trench semiconductor device of claim 2, further comprising a plurality of intermediate trench portions between the exterior trench pattern and the interior trench pattern, the plurality of intermediate trench portions at least partially surrounding the interior trench pattern.
 4. The trench semiconductor device of claim 2, wherein the exterior trench pattern is formed with the plurality of exterior trench portions separated from one another by gaps therebetween.
 5. The trench semiconductor device of claim 2, wherein the exterior trench pattern is formed with at least one notch feature located adjacent to openings between legs of the snake pattern formed by the plurality of first interior trench portions and the plurality of second interior trench portions.
 6. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a plurality of separated closed rectangles.
 7. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a pattern having an outer frame and a plurality of vertical trench legs connecting top and bottom horizontal segments of the outer frame.
 8. The trench semiconductor device of claim 1, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a grid pattern.
 9. The trench semiconductor device of claim 8, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form the grid pattern with the plurality of first interior trench portions including extensions that extend beyond an outer rectangular perimeter of the grid pattern.
 10. The trench semiconductor device of claim 8, wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form the grid pattern with an offset such successive columns of horizontal legs of the grid pattern formed by the plurality of second interior trench portions connecting adjacent vertical legs of the grid pattern formed by the plurality of first interior trench portions are offset from one another.
 11. A trench semiconductor device comprising: a layer of semiconductor material; an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material; and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material, arranged at angles to each other and connected to each other to form a plurality of six sided polygons.
 12. The trench semiconductor device of claim 11, wherein the six sided polygons are arranged in a honeycomb pattern.
 13. The trench semiconductor device of claim 11, wherein the plurality of interior trench portions are arranged at angles to each other and connected to each other to form a geometric pattern including plurality of six sided polygons and at least one eight sided polygon.
 14. A trench semiconductor device comprising: a layer of semiconductor material; an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of exterior trench portions being formed as a plurality of separated exterior trench segments; and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of interior trench portions being formed as a plurality of parallel vertical trench legs. 